The present invention relates to digital interface systems for interfacing microprocessors to digital-to-analog converters and more particularly to such a system wherein multi-channel, simultaneous analog outputs can be obtained, avoiding sequential addressing delays.
In many microprocessor applications, the microcomputer is required to supply more than one output channel. In analog applications where digital information from the microcomputer must be converted to multi-channel analog outputs, interfacing circuitry is added between the microprocessor and the digital-to-analog converter for each output channel. Straightforward multiplexing techniques include interface circuitry comprising a data latch for each channel, i.e., for each D/A converter, and a control logic circuit for sequentially addressing the different channels. Under software control, the microcomputer enables and loads the latch associated with a particular output channel. The "latched" digital information is simultaneously presented to the corresponding D/A converter. Inherent in such an interfacing technique, however, are sequential addressing delays with respect to the various output channels. Thus, if it is desired to obtain multi-channel, simultaneous analog outputs (to control a set of servo-actuators, for instance), the straightforward multiplex technique will not perform the task.